Before Qimonda’s unfortunate demise last year, they delivered an impressive paper at IEDM [1] describing a “buried wordline” (BwL). Memory chip supplier Qimonda says it is about to begin commercial production of DRAM chips using its new “Buried Wordline” technology. Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce.

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The buried word line may be formed using a chemical vapor deposition, a physical vapor deposition PVDor an atomic layer deposition method. Thus, the regions illustrated in the figures are schematic in nature and their shapes may be not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

This has the dual advantages of a leaner, thus cheaper, process, and also reduced power consumption, since there is less parasitic capacitance between the bitlines and the wordlines see below. In example embodiments, the gate electrode layer may be formed to have a thickness within a range of about 1 to about 10 nm.

The upper buried word line may be formed by recessing the polished second word line layer into the substrate It will be understood that, although the terms first, second, third etc. The semiconductor device of claim 1wherein the gate insulating layer is a thermal oxide layer.

6F2 buried wordline DRAM cell for 40nm and beyond – Semantic Scholar

Semiconductor device including a field effect transistor and method of forming thereof. The top surfaces of the gate insulating layerthe gate electrode layerand the buried word line formed on the gate electrode buroed may be formed so as to not protrude beyond the top surface of the substratee. For example, in order to secure a step coverage above The upper buried word line may be formed of any one of tungsten Waluminum Alcupper Cumolybdenum Motitanium Titantalum Taand ruthenium Ruor a combination thereof.

These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section.

Transistor having dual work function bruied gate electrode, method for manufacturing worsline same and electronic device having the same. Extension Media websites place cookies on your device to give you the best user experience. Likewise, a buried region formed by dordline may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

The semiconductor device of claim 1wherein the lower buried word line includes at least one of tungsten Waluminum Alcupper Cumolybdenum Motitanium Titantalum Taand ruthenium Ru.

Winbond Adopts Qimonda’s Buried Wordline Technology – Metal Gates Come to DRAMs | Siliconica

Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments. Therefore, it is to be understood that the foregoing is illustrative of example embodiments and is not to be construed as limited to the specific embodiments disclosed, and that bugied to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.

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The capping layer may be formed after forming the buried word line having the buried word line structure. One other point was made by Qimonda before they went under, that this technology is particularly suitable for a cell shrink from the current 6F2 to a 4F2 format, enabling even more cost savings by reducing die size.

The upper buried wlrdline line may comprise a silicide. Accordingly, when the gate electrode layer includes polysilicon and is formed to a thickness of about 5 nm, the atomic layer deposition may be carried out using the Si 3 H 8 gas.

Semiconductor buired and manufacturing method to avoid the problem of hammering column. SUMMARY Example embodiments provide a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried inside of a substrate, thereby reducing the height of the semiconductor device and the degradation of oxide layers due to the application of a TiN metal gate.

6F2 buried wordline DRAM cell for 40nm and beyond

Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same. Dual work function bruied gate type transistor, method for manufacturing the same and electronic device having the same.

Although example embodiments have been described, those skilled in the art will readily appreciate sordline many modifications are possible in example embodiments without materially departing from the novel teachings and advantages of example embodiments. Accordingly, all such modifications are intended to be included within the scope of the claims.

The forming of the buried word line may comprise forming the lower buried word line in the lower region of the gate electrode layer, and forming the upper buried word line in the upper region of the gate electrode layer. Therefore, in the above structure, the semiconductor device having a height corresponding to the protruded portion of the metal gate electrode 20 is formed.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. In example embodiments, the gate insulating layer may be a thermal oxide layer formed by thermal oxidation. In general, when thinly forming a polysilicon layer using an atomic layer deposition method, SiH 4 gas or Si 2 H 6 gas may be used as bufied silicon source gas.

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. The gate insulating layer may be a thermal oxide layer formed by buroed oxidation.

In example embodiments, the buried word line may include any one selected from the group consisting of tungsten Waluminum Alcupper Cumolybdenum Motitanium Titantalum Taand ruthenium Ruor a combination thereof. Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same.

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Spacers 24 are formed on both sides of the protruded metal gate electrode 20and a capping pattern 22 is disposed on the upper surface of metal bruied electrode The trench may have a width within a range of about 10 to about nm.

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‘Buried Wordline’ DRAM becomes reality

The metal gate electrode 20 can serve as a gate electrode wordkine a word line. The semiconductor device of claim 1further comprising: Semiconductor device including a metal gate electrode formed in a trench and method of forming thereof. Semiconductor integrated circuit device capable of securing gate performance and channel length.

However, this is merely illustrative and thus, the gate electrode layer and the buried word line are not limited to this recessed feature. Wordlin semiconductor device having the buried metal gate electrode structure having a low resistance and a method of manufacturing the same.

As such, the deposition of the metal that forms the upper buried word worrline may be performed more easily. The lower buried word line may be formed by recessing the polished first word line layer into the substrate The Qimonda slide below shows the difference in structure; on the left is the buried wordline in redsunk into the substrate silicon, and on burieed right is an oriental competitor using a spherical recess-channel transistor with the tungsten part of the gate highlighted in red.

Such technique is well known to those skilled in the art and thus, the detailed description thereof is omitted. As described above, the electrical resistance of the word line of the buried word line composed of the lower buried word line and the upper buried word line may be lower when the upper buried word line includes silicide and metal material.

A metal gate electrode 20which fills the trench 14 wordlinr the gate insulating layer 16 and protrudes beyond the substrate 10is formed. The device may be otherwise oriented rotated 90 degrees or at other burked and the spatially relative descriptors used herein interpreted accordingly.

The semiconductor device of claim biriedwherein the trench has a width within wordlie range of about 10 to about nm. The semiconductor device of claim 1wherein the gate electrode layer has a thickness within a range of about 1 to about 10 nm. Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong.

Elpida has also licensed the process, so given the cost and performance advantages, we can likely look forward to BwL product from Japan; and who knows what other manufacturers might go that way?